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PRELIMINARY
CY7C1352G
4-Mbit (256Kx18) Pipelined SRAM with NoBLTM Architecture
Features
* Pin compatible and functionally equivalent to ZBTTM devices * Internally self-timed output buffer control to eliminate the need to use OE * Byte Write capability * 256K x 18 common I/O architecture * Single 3.3V power supply * 2.5V / 3.3V I/O Operation * Fast clock-to-output times * 2.6 ns (for 250-MHz device) * 2.8 ns (for 200-MHz device) * 3.5 ns (for 166-MHz device) * 4.0 ns (for 133-MHz device) * Clock Enable (CEN) pin to suspend operation * Synchronous self-timed writes * Asynchronous output enable (OE) * Pb-Free 100 TQFP package * Burst Capability--linear or interleaved burst order * ZZ" Sleep Mode Option and Stop Clock option
Functional Description[1]
The CY7C1352G is a 3.3V, 256K x 18 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1352G is equipped with the advanced No Bus LatencyTM (NoBLTM) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of the SRAM, especially in systems that require frequent Write/Read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable (CEN) signal, which, when deasserted, suspends operation and extends the previous clock cycle. Maximum access delay from the clock rise is 2.6 ns (250-MHz device). Write operations are controlled by the two Byte Write Select (BW[A:B]) and a Write Enable (WE) input. All writes are conducted with on-chip synchronous self-timed write circuitry. Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output tri-state control. In order to avoid bus contention, the output drivers are synchronously tri-stated during the data portion of a write sequence.
Logic Block Diagram
A0, A1, A MODE CLK CEN C
WRITE ADDRESS REGISTER 1
ADDRESS REGISTER 0
A1 A1' D1 Q1 A0 A0' BURST D0 Q0 LOGIC ADV/LD C
WRITE ADDRESS REGISTER 2
ADV/LD BWA BWB WE
WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC WRITE DRIVERS MEMORY ARRAY
S E N S E A M P S
O U T P U T R E G I S T E R S
D A T A S T E E R I N G
O U T P U T B U F F E R S
DQs DQPA DQPB
E
E
INPUT REGISTER 1
E
INPUT REGISTER 0
E
OE CE1 CE2 CE3 ZZ
READ LOGIC
Sleep Control
Notes: 1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation Document #: 38-05514 Rev. *A
*
3901 North First Street
*
San Jose, CA 95134 * 408-943-2600 Revised November 10, 2004
PRELIMINARY
Selection Guide
Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current 250 MHz 2.6 325 40 200 MHz 2.8 265 40 166 MHz 3.5 240 40
CY7C1352G
133 MHz 4.0 225 40
Unit ns mA mA
Shaded area contains advance information. Please contact your local Cypress sales representative for availability of these parts.
Pin Configuration
100-Pin TQFP
ADV/LD BWB BWA CE1 CE2 CE3 VDD VSS CEN CLK WE
NC NC NC
OE
A
A
NC
A 82
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
NC NC NC VDDQ VSS NC NC DQB DQB VSS VDDQ DQB DQB NC BYTE B VDD NC VSS DQB DQB VDDQ VSS DQB DQB DQPB NC VSS VDDQ NC NC NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
100
81
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
A
A NC NC VDDQ VSS NC DQPA DQA DQA VSS VDDQ DQA DQA VSS NC VDD ZZ DQA DQA VDDQ VSS DQA DQA NC NC VSS VDDQ NC NC NC BYTE A
CY7C1352G
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49 A
VDD
MODE
VSS
NC
NC
NC
A1
A0
NC
A
A
A
A
A
A
A
A
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A
A
50
Page 2 of 13
PRELIMINARY
Pin Definitions
Name A0, A1, A BW[A:B] WE ADV/LD I/O InputSynchronous InputSynchronous InputSynchronous InputSynchronous Description
CY7C1352G
Address Inputs used to select one of the 256K address locations. Sampled at the rising edge of the CLK. A[1:0] are fed to the two-bit burst counter. Byte Write Inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on the rising edge of CLK. Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal must be asserted LOW to initiate a write sequence. Advance/Load Input. Used to advance the on-chip address counter or load a new address. When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address can be loaded into the device for an access. After being deselected, ADV/LD should be driven LOW in order to load a new address. Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is only recognized if CEN is active LOW. Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 and CE3 to select/deselect the device. Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3 to select/deselect the device. Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select/deselect the device. Output Enable, asynchronous input, active LOW. Combined with the synchronous logic block inside the device to control the direction of the I/O pins. When LOW, the DQ pins are allowed to behave as outputs. When deasserted HIGH, DQ pins are tri-stated, and act as input data pins. OE is masked during the data portion of a write sequence, during the first clock when emerging from a deselected state, when the device has been deselected. Clock Enable Input, active LOW. When asserted LOW the Clock signal is recognized by the SRAM. When deasserted HIGH the Clock signal is masked. Since deasserting CEN does not deselect the device, CEN can be used to extend the previous cycle when required. ZZ "sleep" Input. This active HIGH input places the device in a non-time-critical "sleep" condition with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ pin has an internal pull-down. Bidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the address during the clock rise of the read cycle. The direction of the pins is controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH, DQs and DQP[A:B] are placed in a tri-state condition. The outputs are automatically tri-stated during the data portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of OE. Bidirectional Data Parity I/O Lines. Functionally, these signals are identical to DQs. During write sequences, DQP[A:B] is controlled by BW[A:B] correspondingly.
CLK CE1 CE2 CE3 OE
Input-Clock InputSynchronous InputSynchronous InputSynchronous InputAsynchronous
CEN
InputSynchronous InputAsynchronous I/OSynchronous
ZZ
DQs
DQP[A:B] MODE
I/OSynchronous
Input Strap Pin Mode Input. Selects the burst order of the device. When tied to Gnd selects linear burst sequence. When tied to VDD or left floating selects interleaved burst sequence. Power Supply Ground Power supply inputs to the core of the device. Ground for the device. No Connects. Not internally connected to the die. I/O Power Supply Power supply for the I/O circuitry.
VDD VDDQ VSS NC
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PRELIMINARY
Functional Overview
The CY7C1352G is a synchronous-pipelined Burst SRAM designed specifically to eliminate wait states during Write/Read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock signal is qualified with the Clock Enable input signal (CEN). If CEN is HIGH, the clock signal is not recognized and all internal states are maintained. All synchronous operations are qualified with CEN. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (tCO) is 2.6 ns (250-MHz device). Accesses can be initiated by asserting all three Chip Enables (CE1, CE2, CE3) active at the rising edge of the clock. If Clock Enable (CEN) is active LOW and ADV/LD is asserted LOW, the address presented to the device will be latched. The access can either be a read or write operation, depending on the status of the Write Enable (WE). BW[A:B] can be used to conduct byte write operations. Write operations are qualified by the Write Enable (WE). All writes are simplified with on-chip synchronous self-timed write circuitry. Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE) simplify depth expansion. All operations (Reads, Writes, and Deselects) are pipelined. ADV/LD should be driven LOW once the device has been deselected in order to load a new address for the next operation. Single Read Accesses A read access is initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2, and CE3 are ALL asserted active, (3) the Write Enable input signal WE is deasserted HIGH, and (4) ADV/LD is asserted LOW. The address presented to the address inputs is latched into the Address Register and presented to the memory core and control logic. The control logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At the rising edge of the next clock the requested data is allowed to propagate through the output register and onto the data bus, provided OE is active LOW. After the first clock of the read access the output buffers are controlled by OE and the internal control logic. OE must be driven LOW in order for the device to drive out the requested data. During the second clock, a subsequent operation (Read/Write/Deselect) can be initiated. Deselecting the device is also pipelined. Therefore, when the SRAM is deselected at clock rise by one of the chip enable signals, its output will tri-state following the next clock rise. Burst Read Accesses The CY7C1352G has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four Reads without reasserting the address inputs. ADV/LD must be driven LOW in order to load a new address into the SRAM, as described in the Single Read Access section above. The sequence of the burst counter is determined by the MODE
CY7C1352G
input signal. A LOW input on MODE selects a linear burst mode, a HIGH selects an interleaved burst sequence. Both burst counters use A0 and A1 in the burst sequence, and will wrap-around when incremented sufficiently. A HIGH input on ADV/LD will increment the internal burst counter regardless of the state of chip enables inputs or WE. WE is latched at the beginning of a burst cycle. Therefore, the type of access (Read or Write) is maintained throughout the burst sequence. Single Write Accesses Write accesses are initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2, and CE3 are ALL asserted active, and (3) the write signal WE is asserted LOW. The address presented to the address inputs is loaded into the Address Register. The write signals are latched into the Control Logic block. On the subsequent clock rise the data lines are automatically tri-stated regardless of the state of the OE input signal. This allows the external logic to present the data on DQs and DQP[A:B]. In addition, the address for the subsequent access (Read/Write/Deselect) is latched into the Address Register (provided the appropriate control signals are asserted). On the next clock rise the data presented to DQs and DQP[A:B] (or a subset for byte write operations, see Write Cycle Description table for details) inputs is latched into the device and the write is complete. The data written during the Write operation is controlled by BW[A:B] signals. The CY7C1352G provides byte write capability that is described in the Write Cycle Description table. Asserting the Write Enable input (WE) with the selected Byte Write Select (BW[A:B]) input will selectively write to only the desired bytes. Bytes not selected during a byte write operation will remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations. Byte write capability has been included in order to greatly simplify Read/Modify/Write sequences, which can be reduced to simple byte write operations. Because the CY7C1352G is a common I/O device, data should not be driven into the device while the outputs are active. The Output Enable (OE) can be deasserted HIGH before presenting data to the DQs and DQP[A:B] inputs. Doing so will tri-state the output drivers. As a safety precaution, DQs and DQP[A:B] are automatically tri-stated during the data portion of a write cycle, regardless of the state of OE. Burst Write Accesses The CY7C1352G has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four Write operations without reasserting the address inputs. ADV/LD must be driven LOW in order to load the initial address, as described in the Single Write Access section above. When ADV/LD is driven HIGH on the subsequent clock rise, the chip enables (CE1, CE2, and CE3) and WE inputs are ignored and the burst counter is incremented. The correct BW[A:B] inputs must be driven in each cycle of the burst write in order to write the correct bytes of data.
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PRELIMINARY
Sleep Mode The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation "sleep" mode. Two clock cycles are required to enter into or exit from this "sleep" mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the "sleep" mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the "sleep" mode. CE1, CE2, and CE3, must remain inactive for the duration of tZZREC after the ZZ input returns LOW.
CY7C1352G
Interleaved Burst Address Table (MODE = Floating or VDD)
First Address A1, A0 00 01 10 11 Second Address A1, A0 01 00 11 10 Third Address A1, A0 10 11 00 01 Fourth Address A1, A0 11 10 01 00
Linear Burst Address Table (MODE = GND)
First Address A1, A0 00 01 10 11 Second Address A1, A0 01 10 11 00 Third Address A1, A0 10 11 00 01 Fourth Address A1, A0 11 00 01 10
Truth Table [2, 3, 4, 5, 6, 7, 8]
Operation Deselect Cycle Continue Deselect Cycle Read Cycle (Begin Burst) Read Cycle (Continue Burst) NOP/Dummy Read (Begin Burst) Dummy Read (Continue Burst) Write Cycle (Begin Burst) Write Cycle (Continue Burst) NOP/WRITE ABORT (Begin Burst) WRITE ABORT (Continue Burst) IGNORE CLOCK EDGE (Stall) SNOOZE MODE Address Used None None External Next External Next External Next None Next Current None CE H X L X L X L X L X X X ZZ L L L L L L L L L L L H ADV/LD L H L H L H L H L H X X WE X X H X H X L X L X X X BWx X X X X X X L L H H X X OE X X L L H H X X X X X X CEN L L L L L L L L L L H X CLK L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H X DQ tri-state tri-state Data Out (Q) Data Out (Q) tri-state tri-state Data In (D) Data In (D) tri-state tri-state - tri-state
Notes: 2. X="Don't Care." H= Logic HIGH, L =Logic LOW. CE stands for ALL Chip Enables active. BWX = L signifies at least one Byte Write Select is active, BWX = Valid signifies that the desired byte write selects are asserted, see Write Cycle Description table for details. 3. Write is defined by BW[A:B], and WE. See Write Cycle Descriptions table. 4. When a write cycle is detected, all I/Os are tri-stated, even during byte writes. 5. The DQ and DQP pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock. 6. CEN = H, inserts wait states. 7. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE. 8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQP[A:B] = tri-state when OE is inactive or when the device is deselected, and DQs and DQP[A:B] = data when OE is active.
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PRELIMINARY
Truth Table for Read/Write [ 2, 3]
Function Read Write - No bytes written Write Byte A - (DQA and DQPA) Write Byte B - (DQB and DQPB) Write All Bytes WE H L L L L BWB X H H L L
CY7C1352G
BWA X H L H L
ZZ Mode Electrical Characteristics
Parameter IDDZZ tZZS tZZREC tZZI tRZZI Description Snooze mode standby current Device operation to ZZ ZZ recovery time ZZ active to snooze current ZZ inactive to exit snooze current Test Conditions ZZ > VDD - 0.2V ZZ > VDD - 0.2V ZZ < 0.2V This parameter is sampled This parameter is sampled 0 2tCYC 2tCYC Min. Max. 40 2tCYC Unit mA ns ns ns ns
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PRELIMINARY
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ..................................... -65C to +150C Ambient Temperature with Power Applied.................................................. -55C to +125C Supply Voltage on VDD Relative to GND.........-0.5V to +4.6V DC Voltage Applied to Outputs in tri-state ..................................................-0.5V to VDDQ + 0.5V DC Input Voltage ...................................... -0.5V to VDD + 0.5V
CY7C1352G
Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current.................................................... > 200 mA
Operating Range
Range Com'l Ind'l Ambient Temperature (TA) 0C to +70C -40C to +85C VDD VDDQ
3.3V - 5%/+10% 2.5V -5% to VDD
Electrical Characteristics Over the Operating Range [9, 10]
Parameter VDD VDDQ VOH VOL VIH VIL IX Description Power Supply Voltage I/O Supply Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Input LOW Voltage[9] Voltage[9] VDDQ = 3.3V, VDD = Min., IOH = -4.0 mA VDDQ = 2.5V, VDD = Min., IOH = -1.0 mA VDDQ = 3.3V, VDD = Min., IOL = 8.0 mA VDDQ = 2.5V, VDD = Min., IOL = 1.0 mA VDDQ = 3.3V VDDQ = 2.5V VDDQ = 3.3V VDDQ = 2.5V Input Load Current except ZZ GND VI VDDQ and MODE Input Current of MODE Input Current of ZZ IOZ IDD Output Leakage Current VDD Operating Supply Current Input = VSS Input = VDD Input = VSS Input = VDD GND VI VDDQ, Output Disabled VDD = Max., IOUT = 0 mA, f = fMAX = 1/tCYC 4-ns cycle, 250 MHz 5-ns cycle, 200 MHz 6-ns cycle, 166 MHz 7.5-ns cycle, 133 MHz ISB1 Automatic CE Power-Down Current--TTL Inputs VDD = Max, Device Deselected, 4-ns cycle, 250 MHz VIN VIH or VIN VIL 5-ns cycle, 200 MHz f = fMAX = 1/tCYC 6-ns cycle, 166 MHz 7.5-ns cycle, 133 MHz ISB2 Automatic CE Power-down Current--CMOS Inputs VDD = Max, Device Deselected, All speeds VIN 0.3V or VIN > VDDQ - 0.3V, f = 0 -5 -5 30 5 325 265 240 225 120 110 100 90 40 2.0 1.7 -0.3 -0.3 -5 -30 5 Test Conditions Min. 3.135 2.375 2.4 2.0 0.4 0.4 VDD + 0.3V VDD + 0.3V 0.8 0.7 5 Max. 3.6 VDD Unit V V V V V V V V V V A A A A A A mA mA mA mA mA mA mA mA mA
Shaded areas contain advance information. Notes: 9. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC)> -2V (Pulse width less than tCYC/2). 10. TPower-up: Assumes a linear ramp from 0V to VDD (min.) within 200ms. During this time VIH < VDD and VDDQ < VDD.
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PRELIMINARY
Electrical Characteristics Over the Operating Range [9, 10] (continued)
Parameter ISB3 Description Automatic CE Power-down Current--CMOS Inputs Test Conditions VDD = Max, Device Deselected, 4-ns cycle, 250 MHz or VIN 0.3V or VIN > VDDQ - 5-ns cycle, 200 MHz 0.3V 6-ns cycle, 166 MHz f = fMAX = 1/tCYC 7.5-ns cycle, 133 MHz VDD = Max, Device Deselected, All speeds VIN VIH or VIN VIL, f = 0 Min.
CY7C1352G
Max. 105 95 85 75 45 Unit mA mA mA mA mA
ISB4
Automatic CE Power-down Current--TTL Inputs
Thermal Resistance[11]
Parameter JA JC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA / JESD51. TQFP Package TBD TBD Unit C/W C/W
Capacitance[11]
Parameter CIN CCLK CI/O Description Input Capacitance Clock Input Capacitance Input/Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VDD = 3.3V, VDDQ = 3.3V Max. 5 5 5 Unit pF pF pF
AC Test Loads and Waveforms
3.3V I/O Test Load
OUTPUT Z0 = 50 3.3V OUTPUT RL = 50 5 pF R = 351 R = 317 ALL INPUT PULSES VDDQ 10% GND 1 ns 90% 90% 10% 1 ns 1ns
VT = 1.5V
(a) 2.5V I/O Test Load
OUTPUT Z0 = 50 2.5V
INCLUDING JIG AND SCOPE
(b)
R = 1667 VDDQ 10% GND R =1538 1 ns
(c)
ALL INPUT PULSES 90% 90% 10% 1 ns
OUTPUT RL = 50 VT = 1.25V 5 pF INCLUDING JIG AND SCOPE
(a)
(b)
(c)
Note: 11. Tested initially and after any design or process changes that may affect these parameters.
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PRELIMINARY
Switching Characteristics Over the Operating Range [16, 17]
250 MHz Parameter tPOWER Clock tCYC tCH tCL Output Times tCO tDOH tCLZ tCHZ tOEV tOELZ tOEHZ Set-up Times tAS tALS tWES tCENS tDS tCES Hold Times tAH tALH tWEH tCENH tDH tCEH Address Hold After CLK Rise ADV/LD Hold after CLK Rise GW, BW[A:B] Hold After CLK Rise CEN Hold After CLK Rise Data Input Hold After CLK Rise Chip Enable Hold After CLK Rise 0.3 0.3 0.3 0.3 0.3 0.3 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 Address Set-up Before CLK Rise ADV/LD Set-up Before CLK Rise GW, BW[A:B] Set-Up Before CLK Rise CEN Set-up Before CLK Rise Data Input Set-up Before CLK Rise Chip Enable Set-up Before CLK Rise 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.5 1.5 1.5 1.5 1.5 1.5 Data Output Valid After CLK Rise Data Output Hold After CLK Rise Clock to Low-Z[13, 14, 15] Clock to High-Z[13, 14, 15] Low-Z[13, 14, 15] High-Z[13, 14, 15] 0 2.6 OE LOW to Output Valid OE LOW to Output OE HIGH to Output 1.0 0 2.6 2.6 0 2.8 2.6 1.0 0 2.8 2.8 0 3.5 2.8 1.5 0 3.5 3.5 3.5 Clock Cycle Time Clock HIGH Clock LOW 4.0 1.7 1.7 5.0 2.0 2.0 6.0 2.5 2.5 Description VDD (typical) to the first Access[12] Min. 1 Max 200 MHz Min. 1 Max 166 MHz Min. 1 Max
CY7C1352G
133 MHz Min. 1 7.5 3.0 3.0 4.0 1.5 0 4.0 4.0 0 4.0 1.5 1.5 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 0.5 0.5 Max Unit ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Shaded areas contain advance information. Notes: 12. This part has a voltage regulator internally; tpower is the time that the power needs to be supplied above VDD minimum initially before a read or write operation can be initiated. 13. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured 200 mV from steady-state voltage. 14. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve tri-state prior to Low-Z under the same system conditions. 15. This parameter is sampled and not 100% tested. 16. Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V. 17. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
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PRELIMINARY
Switching Waveforms
Read/Write Timing[18, 19, 20]
CY7C1352G
1 CLK
tCENS tCENH
2
t CYC
3
4
5
6
7
8
9
10
tCH
tCL
CEN
tCES tCEH
CE ADV/LD WE BW[A:B] ADDRESS
tAS
A1
tAH
A2
tDS tDH
A3
A4
tCO tCLZ tDOH
A5
tOEV
A6
tCHZ
A7
Data In-Out (DQ)
D(A1)
D(A2)
D(A2+1)
Q(A3)
Q(A4)
tOEHZ
Q(A4+1)
D(A5)
Q(A6)
tDOH
OE
WRITE D(A1) WRITE D(A2) BURST WRITE D(A2+1) READ Q(A3) READ Q(A4) BURST READ Q(A4+1) WRITE D(A5)
tOELZ
READ Q(A6)
WRITE D(A7)
DESELECT
DON'T CARE
UNDEFINED
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PRELIMINARY
Switching Waveforms (continued)
NOP, STALL, and DESELECT Cycles[18, 19, 21]
CY7C1352G
1 CLK CEN CE ADV/LD WE BW[A:B] ADDRESS Data In-Out (DQ)
WRITE D(A1)
2
3
4
5
6
7
8
9
10
A1
A2
A3 D(A1)
A4 Q(A2)
WRITE D(A4)
A5
tCHZ
Q(A3)
STALL NOP
D(A4)
READ Q(A5) DESELECT
Q(A5)
CONTINUE DESELECT
READ Q(A2)
STALL
READ Q(A3)
DON'T CARE
ZZ Mode Timing[22, 23]
CLK
t ZZ
UNDEFINED
t ZZREC
ZZ
t
ZZI
I
SUPPLY I DDZZ t RZZI DESELECT or READ Only
ALL INPUTS (except ZZ)
Notes: 18. For this waveform ZZ is tied low. 19. When CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH. 20. Order of the Burst sequence is determined by the status of the MODE (0= Linear, 1= Interleaved). Burst operations are optional. 21. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle. 22. Device must be deselected when entering ZZ mode. See cycle description table for all possible signal conditions to deselect the device. 23. DQs are in high-Z when exiting ZZ sleep mode.
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PRELIMINARY
Ordering Information
Speed (MHz) 250 200 166 133 Ordering Code CY7C1352G-250AXC CY7C1352G-250AXI CY7C1352G-200AXC CY7C1352G-200AXI CY7C1352G-166AXC CY7C1352G-166AXI CY7C1352G-133AXC CY7C1352G-133AXI Package Name A101 A101 A101 A101 A101 A101 A101 A101 Package Type
CY7C1352G
Operating Range Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial
Lead-Free 100-Lead Thin Quad Flat Pack(14 x 20 x 1.4mm) Lead-Free 100-Lead Thin Quad Flat Pack(14 x 20 x 1.4mm) Lead-Free 100-Lead Thin Quad Flat Pack(14 x 20 x 1.4mm) Lead-Free 100-Lead Thin Quad Flat Pack(14 x 20 x 1.4mm) Lead-Free 100-Lead Thin Quad Flat Pack(14 x 20 x 1.4mm) Lead-Free 100-Lead Thin Quad Flat Pack(14 x 20 x 1.4mm) Lead-Free 100-Lead Thin Quad Flat Pack(14 x 20 x 1.4mm) Lead-Free 100-Lead Thin Quad Flat Pack(14 x 20 x 1.4mm)
Shaded areas contain advance information. Please contact your local cypress sales representative to order parts that are not listed in the ordering information table.
Package Diagram
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
51-85050-*A 51-85050-*A
ZBT is a trademark of Integrated Device Technology. NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. All product and company names mentioned in this document are trademarks of their respective holders.
Document #: 38-05514 Rev. *A
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(c) Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
PRELIMINARY
Document History Page
Document Title: CY7C1352G 4-Mbit (256Kx18) Pipelined SRAM with NoBLTM Architecture Document Number: 38-05514 REV. ** *A ECN NO. Issue Date 224362 288431
See ECN See ECN
CY7C1352G
Orig. of Change RKF VBL New data sheet
Description of Change Deleted 100 MHz and 225 MHz Changed TQFP package in Ordering Information section to lead-free TQFP
Document #: 38-05514 Rev. *A
Page 13 of 13

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